The present application is directed to a semiconductor device, and more particularly, to a semiconductor device with a recess gate (RG) and a method for fabricating the same.
As the integration density of semiconductor devices increases, a channel area is getting smaller, while a doping concentration of an impurity region is getting higher. Thus, an existing planar gate (PG) has difficulty in obtaining characteristics required by high-integrated semiconductor devices, such as threshold voltage and refresh characteristics.
Therefore, to obtain the required threshold voltage and refresh characteristics, a semiconductor device with a recess gate (RG) has been introduced and applied. The recess gate has a three-dimensional channel structure because a gate electrode fills a recess pattern formed in a substrate.
FIG. 1 is a cross-sectional view of a conventional semiconductor device with a recess gate.
Referring to FIG. 1, the conventional semiconductor device with the recess gate includes a substrate 11 with a recess pattern 14, a threshold voltage adjusting layer 15 disposed in the substrate 11 under the recess pattern 14, a gate electrode 17 filling the recess pattern 14 and partially protruding over the substrate 11, gate spacers 20 disposed on both sidewalls of the gate electrode 17, a gate insulation layer 16 disposed between the substrate 11 and the gate electrode 17, and a source/drain region 21 disposed in the substrate 11 on both sides of the gate electrode 17. Also, the semiconductor device includes an isolation layer 12, an active region 13, a gate hard mask layer 18, and a gate 19.
However, as the design rule of a semiconductor device is reduced to 40 nm or less, a leakage current is increased by gate induced drain leakage (GIDL), causing rapid degradation of a refresh characteristic in a semiconductor device.
To solve the degradation of the refresh characteristic caused by GIDL, one proposed method increases a thickness T1 of a region adjacent to the source/drain region 21, that is, the gate insulation layer 16 formed on the sidewall of the recess pattern 14.
However, in case where the thickness T1 of the gate insulation layer 16 formed in a region adjacent to the source/drain region 21 is increased, a thickness of a region adjacent to the threshold voltage adjusting layer 15 (i.e., the gate insulation layer 16 formed on the bottom of the recess pattern 14), is also increased, causing degradation of a threshold voltage characteristic. This degradation is caused because the gate insulation layer 16 is formed using a thermal oxidation or a radical oxidation, and hence, the gate insulation layer 16 formed on the sidewall and bottom of the recess pattern 14 is formed with the same thickness (T1=T2).
Therefore, there is a need for a semiconductor device capable of preventing degradation of a refresh characteristic due to GIDL and obtaining a required threshold voltage characteristic, and a method for fabricating the same.